The use of reduced two's-complement representation in low-power DSP design

Two’s complement signal representation is widely used in the implementation of arithmetic operations. However, it is well-known that its sign-extension can cause undesirable signal transitions in the MSBs of a data-path circuit. We propose a novel technique to reduce the signal transitions due to sign-extension while retaining the simplicity of the two’s complement arithmetic operations. The key idea is to generate a signal representation dynamically according to the signal magnitude. This paper discusses the implementation techniques of using reduced representation in data-path designs. We have applied our proposed techniques in several design examples and our experimental results have shown 13% to 32% power reductions.